HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 315

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 11.30 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 11.30 Cascaded Combinations
Combination
Channels 1 and 2
counters operates independently in phase counting mode.
Cascaded Operation
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
TCNT value
Figure 11.17
Upper 16 Bits
TCNT_1
H'0532
Example of Buffer Operation (2)
11.
Rev.4.00 Mar. 27, 2008 Page 269 of 882
H'0F07
H'0532
Multi-Function Timer Pulse Unit (MTU)
Lower 16 Bits
TCNT_2
H'09FB
H'0F07
REJ09B0108-0400
Time

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