HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 266

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.
11.3.1
The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each
channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR
register settings should be conducted only when TCNT operation is stopped.
Rev.4.00 Mar. 27, 2008 Page 220 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
2
1
0
Multi-Function Timer Pulse Unit (MTU)
Bit Name
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
Timer Control Register (TCR)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Counter Clear 0 to 2
These bits select the TCNT counter clearing source.
See tables 11.3 and 11.4 for details.
Clock Edge 0 and 1
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. Pφ/4 both edges = Pφ/2
rising edge). If phase counting mode is used on
channels 1 and 2, this setting is ignored and the
phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
Pφ/4 or slower. When Pφ/1, or the overflow/underflow
of another channel is selected for the input clock,
although values can be written, counter operation
compiles with the initial value.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
[Legend]
X:
Time Prescaler 0 to 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 11.5 to 11.8 for details.
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