HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 225

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
1
0
Note:
Bit Name Initial Value
NMIF
DME
*
Only 0 can be written to clear the flag.
0
0
R/W
R/(W)*
R/W
Description
NMI Flag
Indicates input of an NMI. This bit is set irrespective
of whether the DMAC is operating or suspended. If
this bit is set during a data transfer, transfers on all
channels are suspended. The CPU is unable to write
a 1 to the NMIF. Clearing is effected by a 0 write
after 1 read.
0: No NMI interrupt, DMA transfer enabled
[Clearing condition]
Write NMIF = 0 after reading NMIF = 1
1: NMI has occurred, DMA transfer prohibited
[Setting condition]
NMI interrupt occurrence
DMAC Master Enable
This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR for the
corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data
transfer, transfers on all channels are suspended.
0: Disable operation on all channels
1: Enable operation on all channels
Even when the DME bit is set, when the TE bit of the
CHCR is 1, or its DE bit is 0, transfer is disabled
when NMI of the DMAOR = 1 or when AE = 1.
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 179 of 882
REJ09B0108-0400