HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 727

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

19.9.2
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block
register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00,
erase protection is set for all blocks.
19.9.3
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory is read during programming/erasing (including vector read and
• Immediately after exception handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase
mode is forcibly aborted at the point when the error is detected. Program mode or erase mode
cannot be re-entered by re-setting the P1 or E1 bit. However, PV and EV bit settings are retained,
Item
SWE bit protect
Block protect
Emulation protect When the RAMS bit in RAMER is set to 1, all
instruction fetch)
Software Protection
Error Protection
Description
When the SWE bit in FLMCR1 is cleared to 0,
all blocks are program/erase-protected. (This
setting should be carried out in on-chip RAM or
external memory.)
By setting the erase block register 1 (EBR1) and
the erase block register 2 (EBR2), erase
protection can be set for individual blocks.
When both EBR1 and EBR2 are set to H'00,
erase protection is set for all blocks.
blocks are program/erase-protected.
Rev.4.00 Mar. 27, 2008 Page 681 of 882
19. Flash Memory (F-ZTAT Version)
Program
Yes
—
Yes
Protect Function
REJ09B0108-0400
Erase
Yes
Yes
Yes