HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 614

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16. Compare Match Timer (CMT)
16.5.3
If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has
priority, so no increment of the write data results on the side on which the write was performed.
The byte data on the side on which writing was not performed is also not incremented, so the
contents are those before the write.
Figure 16.8 shows the timing when an increment occurs during the T2 state of the CMCNT
(Upper byte) write cycle.
Rev.4.00 Mar. 27, 2008 Page 568 of 882
REJ09B0108-0400
Contention between CMCNT Byte Write and Counter Incrementation
Figure 16.8 CMCNT Byte Write and Increment Contention
Address
Internal write
signal
CMCNT input
clock
CMCNT
(Upper byte)
CMCNT
(Lower byte)
Pφ
N
X
CMCNT write cycle
CMCNT (Upper byte)
T1
T2
M
X
CMCNT write data