HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 195

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
7
6
Bit Name Initial Value R/W
CW3
CW2
1
1
R/W
R/W
Description
Idle cycles at continuous access to CS3 and CS7 spaces
This bit inserts an idle cycle and negates the CS3 signal to
make the bus cycle end obvious when accessing the CS3
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS7 space after
access to the CS3 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS7 space, and when access is made to the CS3 space
after access to the CS7 space.
0: No idle cycle inserted at continuous access to the CS3
1: One idle cycle inserted at continuous access to the CS3
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
Idle cycles at continuous access to CS2 and CS6 spaces
This bit inserts an idle cycle and negates the CS2 signal to
make the bus cycle end obvious when accessing the CS2
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS6 space after
access to the CS2 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS6 space, and when access is made to the CS2 space
after access to the CS6 space.
0: No idle cycle inserted at continuous access to the CS2
1: One idle cycle inserted at continuous access to the CS2
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
and CS7 spaces.
and CS7 spaces.
and CS6 spaces.
and CS6 spaces.
Rev.4.00 Mar. 27, 2008 Page 149 of 882
9. Bus State Controller (BSC)
REJ09B0108-0400