HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 272

IC SUPERH MCU ROMLESS 112QFP

HD6417144F50V

Manufacturer Part Number
HD6417144F50V
Description
IC SUPERH MCU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Datasheet

Specifications of HD6417144F50V

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417144F50V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
11.
11.3.3
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU
has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Rev.4.00 Mar. 27, 2008 Page 226 of 882
REJ09B0108-0400
Bit
7
6
5
4
3
2
1
0
Multi-Function Timer Pulse Unit (MTU)
Bit Name
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
Timer I/O Control Register (TIOR)
Initial Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control B0 to B3
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 11.10
TIOR_1:
TIOR_2:
TIORH_3: Table 11.14
TIORH_4: Table 11.16
I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 11.18
TIOR_1:
TIOR_2:
TIORH_3: Table 11.22
TIORH_4: Table 11.24
Table 11.12
Table 11.13
Table 11.20
Table 11.21

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