HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 524

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
Rev.4.00 Mar. 27, 2008 Page 478 of 882
REJ09B0108-0400
Bit
5
4
2
Bit Name Initial Value R/W Description
MST
TRS
C Bus Interface (IIC) Option
0
0
R/W
R/W
Master/Slave Select
Transmission/Reception Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both MST and TRS bits will be cleared by hardware when
they lose in a bus contention in master mode of the I
format. The mode changes to slave receive mode. When
the I
transmission or reception is automatically selected by the
hardware, according to the setting of the R/ W bit of the first
frame after the start condition has been satisfied.
Even if an attempt is made to change the TRS bit during the
transfer of data, the change is suspended until transmission
of data has been completed; the bit is then changed.
[MST clearing conditions]
1. Writing of 0 to this bit by software
2. Lose in a bus contention in master mode of the I
[MST setting conditions]
1. Writing of 1 to this bit by software (MST clearing
2. Writing of 1 to this bit after reading MST = 0 (MST
[TRS clearing conditions]
1. Writing of 0 to this bit by software (except TRS setting
2. Writing of 0 to this bit after TRS = 1 is read (TRS setting
3. Lose in a bus contention in master mode of the I
[TRS setting conditions]
1. Writing of 1 to this bit by software (except TRS clearing
2. Writing of 1 to this bit after reading TRS = 0 (TRS
3. When 1 is received as the R/W bit of the first frame
format
condition 1)
clearing condition 2)
condition 3)
condition 3)
format
condition 3)
clearing condition 3)
address matched in the I
2
C bus format is used in the slave-receive mode,
2
C bus format in slave mode.
2
2
2
C bus
C bus
C bus