HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 579

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. Points for Caution in Setting the Start Condition for Re-transmission
Internal clock
BBSY bit
Figure 14.30 shows the timing and flowchart of the setting of the start condition for re-
transmission, and the timing with which the data is continuously written to ICDR. Write the
transmit data to ICDR after the start condition for re-transmission is issued and then the start
condition is actually generated.
Figure 14.29 Points for Caution in Reading Data Received by Master Reception
SDA
SCL
Bit 0
Master-reception mode
8
(writing 0 to BBSY and SCP)
Execution of the instruction
that sets the stop condition
A
9
ICDR read-disabled
period
Confirmation of stop-condition
(reading 0 from BBSY)
Rev.4.00 Mar. 27, 2008 Page 533 of 882
Stop condition
14. I
(a)
2
C Bus Interface (IIC) Option
Start condition set
REJ09B0108-0400
Start condition