HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 283

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 11.19 TIORL_0 (Channel 0)
[Legend]
X:
Notes: 1. After power-on reset, 0 is output until TIOR is set.
Bit 3
IOC3
0
1
Don’t care
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
Bit 2
IOC2
0
1
0
1
setting is invalid and input capture/output compare is not generated.
Bit 1
IOC1
0
1
0
1
0
1
X
Bit 0
IOC0
0
1
0
1
0
1
0
1
0
1
X
X
TGRC_0
Function
Output
compare
register*
Input
capture
register*
2
2
TIOC0C Pin Function
Output retained*
Initial output is 0
0 output at compare match
Initial output is 0
1 output at compare match
Initial output is 0
Toggle output at compare match
Output retained
Initial output is 1
0 output at compare match
Initial output is 1
1 output at compare match
Initial output is 1
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
11.
Rev.4.00 Mar. 27, 2008 Page 237 of 882
Description
Multi-Function Timer Pulse Unit (MTU)
1
REJ09B0108-0400