HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 416

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11.
11.9.2
Table 11.44 Pin Configuration
Table 11.45 shows output-level comparisons with pin combinations.
Table 11.45 Pin Combinations
11.9.3
The POE has the two registers. The input level control/status register 1 (ICSR1) controls both
POE0 to POE3 pin input signal detection and interrupts. The output level control/status register
(OCSR) controls both the enable/disable of output comparison and interrupts.
Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1)
is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the
enable/disable of interrupts, and indicates status.
Rev.4.00 Mar. 27, 2008 Page 370 of 882
REJ09B0108-0400
Name
Port output enable input pins POE0 to POE3
Pin Combination
PE9/TIOC3B and PE11/TIOC3D
PE12/TIOC4A and PE14/TIOC4C Output
PE13/TIOC4B/MRES and
PE15/TIOC4D/IRQOUT
Multi-Function Timer Pulse Unit (MTU)
Pin Configuration
Register Descriptions
Abbreviation
I/O
Output
Output
Description
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
I/O
Input
Input request signals to make high-
current pins high-impedance state
Description