HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 237

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

10. Direct Memory Access Controller (DMAC)
CK
Transfer source
Transfer destination
A21–A0
address
address
CSn
D15–D0
RD
WRH, WRL
DACK
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
Note:
Transfer between external memories with DACK are output during read cycle.
Figure 10.7 Example of Direct Address Transfer Timing in Dual Address Mode
• Indirect Address Transfer Mode
In this mode the memory address storing the data you actually want to transfer is specified in
DMAC internal transfer source address register (SAR3). Therefore, in indirect address transfer
mode, the DMAC internal transfer source address register value is read first. This value is
stored once in the DMAC. Next, the read value is output as the address, and the value stored at
that address is again stored in the DMAC. Finally, the subsequent read value is written to the
address specified by the transfer destination address register, ending one cycle of DMA
transfer.
In indirect address mode (figure 10.8), transfer destination, transfer source, and indirect
address storage destination are all 16-bit external memory locations, and transfer in this
example is conducted in 16-bit or 8-bit units. Timing for this transfer example is shown in
figure 10.9.
In indirect address mode, one NOP cycle (figure 10.9) is required until the data read as the
indirect address is output to the address bus. When transfer data is 32-bit, the third and fourth
bus cycles each need to be doubled, giving a required total of six bus cycles and one NOP
cycle for the whole operation.
Rev.4.00 Mar. 27, 2008 Page 191 of 882
REJ09B0108-0400