HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 239

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 10.9 Dual Address Mode and Indirect Address Transfer Timing Example
(External Memory Space to External Memory Space, 16-Bit Width)
Notes:
data bus
D15–D0
Internal
A21–A0
address
address
Internal
indirect
DMAC
DMAC
WRH,
buffer
buffer
WRL
CSn
data
bus
RD
CK
1.
2.
The internal address bus is controlled by the port and does not change.
DMAC does not fetch value until 32-bit data is read from the internal data
bus.
Transfer source
address (H)
address (H)
(1st)
address ∗
Transfer
source
Indirect
Address read cycle
Indirect address ∗
1
address (L)
address (L)
(2nd)
Transfer
source
Indirect
NOP
2
cycle
NOP
NOP
10. Direct Memory Access Controller (DMAC)
Indirect
address
Rev.4.00 Mar. 27, 2008 Page 193 of 882
read cycle
Indirect
address
(3rd)
address
Data
Indirect
Transfer
data
Transfer
data
Transfer
write cycle
data
destination
(4th)
Transfer
address
Data
Transfer
Transfer
data
data
REJ09B0108-0400