HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 564

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

14. I
14.4.6
When the address of the slave device matches the address which the master device transfers in the
first frame (address receive frame) after start condition detection in slave receive mode, and the
8th bit of data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and slave transmit
mode is entered.
Figure 14.23 is a flowchart that gives as example of operations in slave transmit mode.
Rev.4.00 Mar. 27, 2008 Page 518 of 882
REJ09B0108-0400
2
C Bus Interface (IIC) Option
No
Clear the IRIC flag in ICCR
Write transmit data to ICDR
Clear the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
No
Read the ACKB bit in ICSR
No
Operations in Slave Transmission
Figure 14.23 Example: Flowchart of Operations in Slave Transmit Mode
Set ACKE to 0 (ICCR)
Slave transmit mode
Set TRS to 0 (ICCR)
(Clear ACKB to 0)
Read ICDR
Transmission
(ACKB = 1?)
completed?
IRIC = 1?
IRIC = 1?
End
Yes
Yes
Yes
[1], [2] If the slave address matches the address in the first frame
[3], [4] Wait for 1 byte to be transmitted.
[4] Determine end of transfer.
[6] Clear the IRIC flag.
[7] Clear acknowledge bit data.
[8] Set slave receive mode.
[9] Dummy read (to release the SCL line).
[10] Wait for stop condition
[3], [5] Set transmit data for the second and subsequent frames.
following the start condition detection and the R/W bit is 1 in slave
receive mode, the mode changes to slave transmit mode.