HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 594

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

15. A/D Converter
15.3.4
The ADTSR enables an A/D conversion started by an external trigger signal.
Rev.4.00 Mar. 27, 2008 Page 548 of 882
REJ09B0108-0400
Bit
2 to 0 —
Bit
7 to 4 —
3
2
1
0
Bit Name
Bit Name
TRG1S1
TRG1S0
TRG0S1
TRG0S0
A/D Trigger Select Register (ADTSR)
All 1
All 0
Initial Value
Initial Value
0
0
0
0
R/W
R
R/W
R
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
AD Trigger 1 Select 1 and 0
Enable the start of A/D conversion by A/D1 with a
trigger signal.
00: A/D conversion start by external trigger pin
01: A/D conversion start by external trigger pin
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the
ADST and TRGE bit in the A/D control registers
(ADCR) to 0.
AD Trigger 0 Select 1 and 0
Enable the start of A/D conversion by A/D0 with a
trigger signal.
00: A/D conversion start by external trigger pin
01: A/D conversion start by external trigger pin
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the
ADST and TRGE bit in the A/D control registers
(ADCR) to 0.
(ADTRG) or MTU trigger is enabled
(ADTRG) is enabled
(ADTRG) or MTU trigger is enabled
(ADTRG) is enabled