HD6417144F50V Renesas Electronics America, HD6417144F50V Datasheet - Page 78

• Manufacturer Part Number: HD6417144F50V
• Description: IC SUPERH MCU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD6417144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2. CPU
2.5
2.5.1
Table 2.10 lists the instructions according to their classification.
Table 2.10 Classification of Instructions
Rev.4.00 Mar. 27, 2008 Page 32 of 882
REJ09B0108-0400
Classification Types
Data transfer
Arithmetic
operations
Instruction Set
Instruction Set by Classification
5
21
Operation
Code
MOV
MOVA
MOVT
SWAP
XTRCT
ADD
ADDC
ADDV
CMP/cond Comparison
DIV1
DIV0S
DIV0U
DMULS
DMULU
DT
EXTS
EXTU
MAC
MUL
MULS
MULU
NEG
NEGC
SUB
Function
Data transfer, immediate data transfer,
peripheral module data transfer, structure data
transfer
Effective address transfer
T bit transfer
Swap of upper and lower bytes
Extraction of the middle of registers connected
Binary addition
Binary addition with carry
Binary addition with overflow check
Division
Initialization of signed division
Initialization of unsigned division
Signed double-length multiplication
Unsigned double-length multiplication
Decrement and test
Sign extension
Zero extension
Multiply-and-accumulate, double-length
multiply-and-accumulate operation
Double-length multiply operation
Signed multiplication
Unsigned multiplication
Negation
Negation with borrow
Binary subtraction
33
No. of
Instructions
39