ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 80

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

80
ATmega16M1/32M1/64M1
• PCINT18/PSCIN2/OC1A/MISO_A, Bit 2
PCSIN2, PSC Digital Input 2.
OC1A, Output Compare Match A output: This pin can serve as an external output for the
Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD2 set “one”)
to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.
MISO_A: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as
a master, this pin is configured as an input regardless of the setting of DDD2. When the SPI is
enabled as a slave, the data direction of this pin is controlled by DDD2. When the pin is forced to
be an input, the pull-up can still be controlled by the PORTD2 bit.
PCINT18, Pin Change Interrupt 18.
• PCINT17/PSCIN0/CLKO – Bit 1
PCSIN0, PSC Digital Input 0.
CLKO, Divided System Clock: The divided system clock can be output on this pin. The divided
system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTD1 and
DDD1 settings. It will also be output during reset.
PCINT17, Pin Change Interrupt 17.
• PCINT16/PSCOUT0A – Bit 0
PSCOUT0A: Output 0 of PSC 0.
PCINT16, Pin Change Interrupt 16.
Table 13-10
ing signals shown in
Table 13-10. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
and
Table 13-11 on page 81
PD7/
ACMP0/
PCINT23
0
0
0
0
0
0
ACMP0D
0
–
ACOMP0
Figure 13-5 on page
PD6/ADC3/
ACMPN2/INT0/
PCINT22
0
0
0
0
0
0
ADC3D + In0en
In0en
INT0
ADC3
ACMPM
relates the alternate functions of Port D to the overrid-
69.
PD5/ADC2/
ACMP2/PCINT21
0
0
0
0
0
0
ADC2D
0
ADC2
ACOMP2
PD4/ADC1/RXD/
RXLIN/ICP1A/
SCK_A/PCINT20
RXEN + SPE •
MSTR • SPIPS
PD4 •
PUD
RXEN + SPE •
MSTR • SPIPS
0
SPE • MSTR •
SPIPS
–
ADC1D
0
ICP1A
ADC1
8209D–AVR–11/10