ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 62

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

12.2.5
12.2.6
62
ATmega16M1/32M1/64M1
PCIFR – Pin Change Interrupt Flag Register
PCMSK3 – Pin Change Mask Register 3
• Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 - PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT26:24 pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23:16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7:0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
• Bit 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 2:0 – PCINT26:24: Pin Change Enable Mask 26:24
Each PCINT26:24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT26:24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23:24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R/W
7
0
-
R
7
–
0
R/W
6
0
-
R
6
–
0
R/W
5
0
-
R
5
–
0
R/W
4
0
-
R
4
–
0
R/W
PCIF3
3
0
-
R
3
0
PCINT26
PCIF2
R/W
R/W
2
0
2
0
PCINT25
PCIF1
R/W
R/W
1
0
1
0
PCINT24
PCIF0
R/W
R/W
0
0
0
0
8209D–AVR–11/10
PCMSK3
PCIFR