ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 228

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

21.5
228
Changing Channel or Reference Selection
ATmega16M1/32M1/64M1
Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion
Figure 21-7. ADC Timing Diagram, Free Running Conversion
Table 21-1.
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last eight ADC clock cycle before the conversion completes
(ADIF in ADCSRA is set). Note that the conversion starts on the second following rising CPU
clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until two ADC clock cycle after ADSC is written.
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
ADC Conversion Time
Prescaler
Reset
MUX and REFS
Update
1
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
2
Conversion
3
Complete
One Conversion
12
First Conversion
4
5
13
Sample &
Hold
13.5
6
25
14
7
One Conversion
Next Conversion
1
Sign and MSB of Result
LSB of Result
8
2
MUX and REFS
Update
3
11
Conversion
Complete
Sample & Hold
Single Ended
Conversion,
4
12
Normal
15.5
5
3.5
13
14
Sign and MSB of Result
LSB of Result
Next Conversion
1
Prescaler
Reset
Auto Triggered
Conversion
2
8209D–AVR–11/10
16
2