ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 167

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

19.3.3.8
19.3.3.9
19.3.3.10
19.3.3.11
19.3.3.12
19.3.4
8209D–AVR–11/10
Arbitration
Bit Lengthening
Bit Shortening
Synchronization Jump Width
Programming the Sample Point
Synchronization
As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2
may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscilla-
tor is slower than the receiver oscillator, the next falling edge used for resynchronization may be
delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of
the bit time.
If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling
edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in
order to adjust the sample point for bit N+1 and the end of the bit time.
The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resyn-
chronization Jump Width.
This segment may not be longer than Phase Segment 2.
Programming of the sample point allows "tuning" of the characteristics to suit the bus.
Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump
Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the
bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such
as ceramic resonators may be used.
Late sampling allows more Time Quanta in the Propagation Time Segment which allows a
poorer bus topology and maximum bus length.
Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit time
is restarted from that edge.
Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Syn-
chronization Segment in a message.
The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple
Access with Arbitration on Message Priority”.
During transmission, arbitration on the CAN bus can be lost to a competing device with a higher
priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmis-
sion was started by more than one node simultaneously and makes sure the most important
message is sent first without time loss.
The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a
data frame and a remote frame with the same identifier are initiated at the same time, the data
frame prevails over the remote frame (c.f. RTR bit).
ATmega16M1/32M1/64M1
167