ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 151

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

17.16.10 PSC Interrupt Mask Register – PIM
8209D–AVR–11/10
• Bit 6 – PISELn: PSC Module n Input Select
Clear this bit to select PSCINn as module n input.
Set this bit to select Comparator n output as module n input.
• Bit 5 – PELEVn: PSC Module n Input Level Selector
When this bit is clear, the low level of selected input generates the significative event for fault
function.
When this bit is set, the high level of selected input generates the significative event for fault
function.
• Bit 4 – PFLTEn: PSC Module n Input Filter Enable
Setting this bit (to one) activates the Input Noise Canceler. When the noise canceler is activated,
the input from the input pin is filtered. The filter function requires four successive equal valued
samples of the input pin for changing its output. The Input is therefore delayed by four oscillator
cycles when the noise canceler is enabled.
• Bit 3 – PAOCn: PSC Module n 0 Asynchronous Output Control
When this bit is clear, Fault input can act directly to PSC module n outputs A & B. See
Section “PSC Input Configuration”, page 142.
• Bit 2:0 – PRFMn2:0: PSC Module n Input Mode
These three bits define the mode of operation of the PSC inputs.
Table 17-12. Input Mode Operation
Bit
Read/Write
Initial Value
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 – PEVE2: PSC External Event 2 Interrupt Enable
When this bit is set, an external event which can generates a a fault on module 2 generates also
an interrupt.
PRFMn2:0
000b
001b
010b
011b
10x
11xb
R
7
0
Description
No action, PSC Input is ignored
Disactivate module n Outputs A
Disactivate module n Output B
Disactivate module n Output A & B
Disactivate all PSC Output
Halt PSC and Wait for Software Action
-
R
6
0
-
R
5
0
-
R
4
0
-
ATmega16M1/32M1/64M1
PEVE2
R/W
3
0
PEVE1
R/W
2
0
PEVE0
R/W
1
0
PEOPE
R/W
0
0
PIM
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