ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 131

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ATMEGA16M1-MU

Manufacturer Part Number
ATMEGA16M1-MU
Description
IC MCU AVR 16K FLASH 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16M1-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
8209D–AVR–11/10
Enabling and disabling of the clock input must be done when Tn/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is
recommended that maximum frequency of an external clock source is less than f
An external clock source can not be prescaled.
Figure 16-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
PSRSYNC
clk
T0
T1
I/O
1. The synchronization logic on the input pins (Tn) is shown in
Synchronization
Synchronization
ExtClk
< f
clk_I/O
/2) given a 50/50% duty cycle. Since the edge detector uses
clk
Clear
T1
ATmega16M1/32M1/64M1
(1)
Figure 16-1 on page 130
clk
clk_I/O
T0
/2.5.
131

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