ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 198

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

20. LIN / UART - Local Interconnect Network Controller or UART
20.1
20.1.1
20.1.2
20.2
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Features
Overview
ATmega16M1/32M1/64M1
LIN
UART
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The LIN (Local Interconnect Network) is a serial communications protocol which efficiently sup-
ports the control of mechatronics nodes in distributed automotive applications. The main
properties of the LIN bus are:
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LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN are
not required. The specification of the line driver/receiver needs to match the ISO9141 NRZ-
standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchronous
serial Receiver and Transmitter (UART).
Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility)
Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow Concept”
of LIN 2.1 Specification
Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames
Automatic LIN Response Handling
Extended LIN Error Detection and Signaling
Hardware Frame Time-out Detection
“Break-in-data” Support Capability
Automatic Re-synchronization to Ensure Proper Frame Integrity
Fully Flexible Extended Frames Support Capabilities
Full Duplex Operation (Independent Serial Receive and Transmit Processes)
Asynchronous Operation
High Resolution Baud Rate Generator
Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames
Data Over-Run and Framing Error Detection
Single master with multiple slaves concept
Low cost silicon implementation based on common UART/SCI interface
Self synchronization in slave node
Deterministic signal transmission with signal propagation time computable in advance
Low cost single-wire implementation
Speed up to 20 Kbit/s.
8209D–AVR–11/10