ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 130

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

16. Timer/Counter0 and Timer/Counter1 Prescalers
16.1
16.2
16.3
130
Internal Clock Source
Prescaler Reset
External Clock Source
ATmega16M1/32M1/64M1
The
(see
prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, that is, operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock
cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system
clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk
The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The syn-
chronized (sampled) signal is then passed through the edge detector.
functional equivalent block diagram of the Tn/T0 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (
parent in the high period of the internal system clock.
The edge detector generates one clk
(CSn2:0 = 6) edge it detects.
Figure 16-1. Tn Pin Sampling
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the Tn/T0 pin to the counter is updated.
CLK_I/O
Tn
clk
“8-bit Timer/Counter0 with PWM”
page
I/O
/1024.
102) share the same prescaler module, but the Timer/Counters can have different
D
LE
CLK_I/O
Q
). Alternatively, one of four taps from the prescaler can be used as a
Synchronization
D
Q
T1
(see
/clk
page
T
0
pulse for each positive (CSn2:0 = 7) or negative
85) and the
CLK_I/O
“16-bit Timer/Counter1 with PWM”
D
Q
/8, f
CLK_I/O
clk
I/O
Edge Detector
Figure 16-1
). The latch is trans-
/64, f
CLK_I/O
8209D–AVR–11/10
Tn_sync
(To Clock
Select Logic)
shows a
T1
/256, or
/clk
T0
).