ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 227

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

8209D–AVR–11/10
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle. See
Selection” on page 228
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.
The actual sample-and-hold takes place 3.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures
a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold
takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-
tional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion com-
pletes, while ADSC remains high. For a summary of conversion times, see
228.
Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 21-5. ADC Timing Diagram, Single Conversion
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADIF
ADCH
ADCL
ADSC
1
1
2
2
MUX and REFS
Update
MUX and REFS
Update
for details on differential conversion timing.
3
12
4
13
5
14
6
Sample & Hold
15
7
Sample & Hold
16
8
First Conversion
ATmega16M1/32M1/64M1
One Conversion
22
23
10
24
11
Conversion
Complete
“Changing Channel or Reference
25
Conversion
12
Complete
26
13
27
14
28
Sign and MSB of Result
Table 21-1 on page
Sign and MSB of Result
LSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
2
MUX and REFS
Update
2
and REFS
3
Update
MUX
3
227