ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 128

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

15.11.7
15.11.8
128
ATmega16M1/32M1/64M1
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7, 6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see
ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
when the OCF1B Flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
when the OCF1A Flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
Flag, located in TIFR1, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
“Interrupt Vectors in ATmega16M1/32M1/64M1” on page
See “Accessing 16-bit Registers” on page 104.
“Interrupt Vectors in ATmega16M1/32M1/64M1” on page
R/W
R
7
0
7
–
0
“Interrupt Vectors in ATmega16M1/32M1/64M1” on page
“Interrupt Vectors in ATmega16M1/32M1/64M1” on page
R/W
R
6
0
6
–
0
ICIE1
R/W
R/W
5
0
5
0
R/W
R
4
–
0
4
0
ICR1[15:8]
ICR1[7:0]
R/W
R
3
–
0
3
0
OCIE1B
R/W
R/W
2
0
2
0
53) is executed when the TOV1
OCIE1A
R/W
R/W
53) is executed when the
1
0
1
0
TOIE1
R/W
R/W
53) is executed
53) is executed
0
0
0
0
8209D–AVR–11/10
TIMSK1
ICR1H
ICR1L