ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 245

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

21.10.5
8209D–AVR–11/10
ADCH and ADCL – ADC Result Data Registers
• Bit 6 – ISRCEN: Current Source Enable
Set this bit to source a 100µA current to the AREF pin.
Clear this bit to use AREF pin as Analog Reference pin.
• Bit 5 – AREFEN: Analog Reference pin Enable
Set this bit to connect the internal AREF circuit to the AREF pin.
Clear this bit to disconnect the internal AREF circuit from the AREF pin.
• Bit 4 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 3:0– ADTS[3:0]: ADC Auto Trigger Source Selection Bits
These bits are only necessary in case the ADC works in auto trigger mode. It means if ADATE
bit in ADCSRA register is set.
In accordance with the
trigger of the start of conversion. The start of conversion will be generated by the rising edge of
the selected interrupt flag whether the interrupt is enabled or not. In case of trig on PSCnASY
event, there is no flag. So in this case a conversion will start each time the trig event appears
and the previous conversion is completed.
Table 21-7.
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
ADTS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADC Auto Trigger Source Selection
Table
21-7, these 3 bits select the interrupt event which will generate the
PSC Module 0 Synchronization Signal
PSC Module 1 Synchronization Signal
PSC Module 2 Synchronization Signal
Timer/Counter1 Compare Match B
Timer/Counter0 Compare Match
Timer/Counter1 Capture Event
ATmega16M1/32M1/64M1
External Interrupt Request 0
Timer/Counter0 Overflow
Timer/Counter1 Overflow
Analog comparator 0
Analog comparator 1
Analog comparator 2
Analog comparator 3
Free Running Mode
Description
Reserved
Reserved
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