ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 215

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

20.5.15
20.5.15.1
20.5.15.2
20.5.16
8209D–AVR–11/10
Data Management
OCD Support
LIN FIFO Data Buffer
UART Data Register
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer
accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the LIN-
DAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can
be read or written. The data index is automatically incremented after each LINDAT access if the
LAINC (active low) bit is cleared. A roll-over is implemented, after data index=7 it is data
index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before each
LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1,
and so on. Nevertheless, LINSEL must be initialized by the user before use.
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be
for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (that is I/O
view behavior in AVR Studio).
1. LINCR:
2. LINSIR:
3. LINENR:
4. LINERR:
5. LINBTR:
6. LINBRRH & LINBRRL:
7. LINDLR:
8. LINIDR:
9. LINSEL:
- LINCR[6..0] are R/W accessible
- LSWRES always is a self-reset bit (needs 1 micro-controller cycle to execute)
- LIDST[2..0] and LBUSY are always Read accessible
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly
by writing 1 or 0)
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR bits
- All bits are R/W accessible
- All bits are R/W accessible
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR
- LBT[5..0] are R/W access only if LDISR is set
- If LDISR is reset, LBT[5..0] are unchangeable
- All bits are R/W accessible
- All bits are R/W accessible
- LID[5..0] are R/W accessible
- LP[1..0] are Read accessible and are always updated on the fly
- All bits are R/W accessible
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