ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 280

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ATMEGA16M1-MU

Manufacturer Part Number
ATMEGA16M1-MU
Description
IC MCU AVR 16K FLASH 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA16M1-MU

Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
CAN, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
26.7.12
26.7.13
280
ATmega16M1/32M1/64M1
Programming Time for Flash when Using SPM
Simple Assembly Code Example for a Boot Loader
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
The calibrated RC Oscillator is used to time Flash accesses.
gramming time for Flash accesses from the CPU.
Table 26-6.
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
1. If there is no need for a Boot Loader update in the system, program the Boot Loader
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
3. Keep the AVR core in Power-down sleep mode during periods of low V
.equ PAGESIZEB = PAGESIZE*2
.org SMALLBOOTSTART
Write_page:
Wrloop:
Lock bits to prevent any Boot Loader software updates
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low V
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient
vent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
; Page Erase
ldi
call Do_spm
; re-enable the RWW section
ldi
call Do_spm
; transfer data from RAM to Flash page buffer
ldi
ldi
ld
ld
ldi
spmcrval, (1<<PGERS) | (1<<SPMEN)
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
looplo, low(PAGESIZEB)
loophi, high(PAGESIZEB)
r0, Y+
r1, Y+
spmcrval, (1<<SPMEN)
SPM Programming Time
Symbol
;PAGESIZEB is page size in BYTES, not words
Min Programming Time
;init loop variable
;not required for PAGESIZEB<=256
3.7ms
Table 26-6
CC
reset protection circuit
Max Programming Time
shows the typical pro-
CC
. This will pre-
4.5ms
8209D–AVR–11/10

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