ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 163

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

19. CAN – Controller Area Network
19.1
19.2
19.3
19.3.1
8209D–AVR–11/10
Features
Overview
CAN Protocol
Principles
•
•
•
•
•
•
The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very
high level of security. The ATmega16M1/32M1/64M1 CAN controller is fully compatible with the
CAN Specification 2.0 Part A and Part B. It delivers the features required to implement the ker-
nel of the CAN bus protocol according to the ISO/OSI Reference Model:
•
•
The CAN controller is able to handle all types of frames (Data, Remote, Error and Overload) and
achieves a bitrate of 1Mbit/s.
The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO
11519-2 for low speed.
CAN is based on a broadcast communication mechanism. This broadcast communication is
achieved by using a message oriented transmission protocol. These messages are identified by
using a message identifier. Such a message identifier has to be unique within the whole network
and it defines not only the content but also the priority of the message.
The priority at which a message is transmitted compared to another less urgent message is
specified by the identifier of each message. The priorities are laid down during system design in
the form of corresponding binary values and cannot be changed dynamically. The identifier with
the lowest binary number has the highest priority.
Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node
observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism,
by which the dominant state overwrites the recessive state. The competition for bus allocation is
lost by all nodes with recessive transmission and dominant observation. All the "losers" automat-
Full CAN Controller
Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B
6 MOb (Message Object) with their own:
1Mbit/s Maximum Transfer Rate at 8MHz
TTC Timer
Listening Mode (for Spying or Autobaud)
The Data Link Layer
The Physical Layer
– 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B)
– 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.0 B)
– 8 Bytes Data Buffer (Static Allocation)
– Tx, Rx, Frame Buffer or Automatic Reply Configuration
– Time Stamping
– the Logical Link Control (LLC) sublayer
– the Medium Access Control (MAC) sublayer
– the Physical Signalling (PLS) sublayer
– not supported - the Physical Medium Attach (PMA)
– not supported - the Medium Dependent Interface (MDI)
ATmega16M1/32M1/64M1
163