ATMEGA16M1-MU Atmel, ATMEGA16M1-MU Datasheet - Page 187

• Manufacturer Part Number: ATMEGA16M1-MU
• Description: IC MCU AVR 16K FLASH 32VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16M1-MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -

19.10.9
8209D–AVR–11/10
CANBT2 – CAN Bit Timing Register 2
• Bit 6:1 – BRP[5:0]: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the individ-
ual bit timing.
If ‘BRP[5..0]=0’, see
ple Point(s)” on page
• Bit 0 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 6:5 – SJW[1:0]: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the control-
ler must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may
be shortened or lengthened by a re-synchronization.
• Bit 4 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 3:1 – PRS[2:0]: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It
is twice the sum of the signal propagation time on the bus line, the input comparator delay and
the output driver delay.
• Bit 0 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
Initial Value
Read/Write
Bit
7
-
-
-
Section 19.5.3 “Baud Rate” on page 172
188.
SJW1
R/W
6
0
SJW0
R/W
5
0
Tprs = Tscl × (PRS [2:0] + 1)
Tscl =
Tsjw = Tscl × (SJW [1:0] + 1)
4
-
-
-
ATmega16M1/32M1/64M1
clk
BRP[5:0] + 1
IO
PRS2
R/W
3
0
frequency
PRS1
R/W
and
2
0
Section • “Bit 0 – SMP: Sam-
PRS0
R/W
1
0
0
-
-
-
CANBT2
187