M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 69

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
NOTES:
Figure 7.5 Bus-using Priorities
Table 7.5 MCU Status in Hold State
BCLK
A0 to A19, D0 to D15, CS0 to CS3, RD, WRL, WRH,
______ ________
WR, BHE
I/O ports
__________
HLDA
Internal peripheral circuits
ALE signal
7.2.8 BCLK Output
Table 7.6 shows the Pin Functions for Each Processor Mode.
7.2.7 HOLD Signal
1. When I/O port function is selected.
2. The watchdog timer does not stop when the PM22 bit in the PM2 register is set to 1 (the count source
the CPU clock is output as BCLK from the BCLK pin. Refer to 8.2 CPU Clock and Peripheral Function
Clock.
This signal is used to transfer control of the bus from the CPU or DMAC to an external circuit. When the
input on HOLD pin is pulled low, the MCU is placed in a hold state after the bus access then in process
finishes. The MCU remains in a hold state while the HOLD pin is held low, during which time the HLDA pin
outputs a low-level signal.
Table 7.5 shows the MCU Status in Hold State.
Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence (see Figure
7.5 Bus-using Priorities). However, if the CPU is accessing an odd address in word units, the DMAC
cannot gain control of the bus during two separate accesses.
If the PM07 bit in the PM0 register is set to 0 (output enable), a clock with the same frequency as that of
for the watchdog timer is the on-chip oscillator clock).
Apr 14, 2006
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page 45 of 376
_______
Item
_______ ______ _________ _________
__________
P0, P1, P3, P4
P6 to P10
__________
HOLD > DMAC > CPU
(1)
__________
Output
High-impedance
High-impedance
Maintains status when hold signal is received
Output “L”
ON (but watchdog timer stops
Undefined
Status
(2)
)
__________
7. Bus