M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 126

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
12.2 DMA Transfer Cycles
Table 12.2 DMA Transfer Cycles
-: This condition does not exist.
Table 12.3 Coefficient j, k
NOTES:
8-bit transfer
(DMBIT =1)
16-bit transfer
(DMBIT = 0)
Any combination of even or odd transfer read and write addresses is possible.
Table 12.2 lists the DMA Transfer Cycles. Table 12.3 lists the Coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
k
j
Transfer Unit
1. Depends on the set value of the PM20 bit in the PM2 register.
2. Depends on the set value of the CSE register.
No Wait With Wait 1 Wait
Internal ROM, RAM
Apr 14, 2006
1
1
Internal Area
2
2
(BYTE = H)
(BYTE = L)
page 102 of 376
(BYTE= H)
(BYTE =L)
Bus Width
16 bits
16 bits
8 bits
8 bits
2
2
(1)
SFR
2 Waits
3
3
Access Address
(1)
Even
Even
Even
Even
No Wait
Odd
Odd
Odd
Odd
1
2
1 Wait 2 Waits 3 Waits 1 Wait 2 Waits 3 Waits
Separate Bus
No. of Read No. of Write No. of Read No. of Write
2
2
Cycles
Single-chip Mode
With Wait
1
1
-
-
1
2
-
-
3
3
External Area
(2)
Cycles
1
1
-
1
2
-
-
-
4
4
Memory Expansion Mode
Microprocessor Mode
3
3
Cycles
Multiplexed Bus
1
1
1
1
1
2
2
2
With Wait
3
3
Cycles
(2)
12. DMAC
1
1
1
1
1
2
2
2
4
4