M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 180

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.13 Transfer Format
15.1.1.4 Continuous Receive Mode
15.1.1.3 LSB First/MSB First Select Function
In continuous receive mode, receive operation becomes enable when the receive buffer register is read.
It is not necessary to write dummy data into the transmit buffer register to enable receive operation in
this mode. However, a dummy read of the receive buffer register is required when starting the operating
mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to 0
(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. Bits U0RRM and U1RRM are bits 2 and 3 in the UCON
register, respectively, and the U2RRM bit is the bit 5 in the U2C1 register.
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
Figure 15.13 shows the Transfer Format.
Apr 14, 2006
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
(2) When the UFORM bit = 1 (MSB first)
i = 0 to 2
* This applies to the case where the CKPOL bit in the UiC0 register = 0
RXDi
CLKi
TXDi
RXDi
CLKi
TXDi
(transmit data output at the falling edge and the receive data taken in at
the rising edge of the transfer clock) and the UiLCH bit in the UiC1
register = 0 (no reverse).
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D0
D0
D7
D7
D1
D6
D1
D6
D2
D5
D2
D5
D3
D4
D3
D4
D4
D4
D3
D3
D5
D5
D2
D2
D6
D1
D6
D1
D7
D0
D7
D0
15. Serial Interface