M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 173

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.9 Registers U0SMR2 to U2SMR2 and U0SMR3 to U2SMR3
UARTi Special Mode Register 2 (i = 0 to 2)
NOTES:
UARTi Special Mode Register 3 (i = 0 to 2)
b7
b7
Apr 14, 2006
1. Bits DL2 to DL0 are used to generate a delay in SDAi output by digital means during I
2. The amount of delay varies with the load on pins SCLi and SDAi. Also, when using an external clock,
b6
b6
In other than I
the amount of delay increases by about 100 ns.
b5
b5
b4
b4
b3
b3
b2
b2
page 149 of 376
2
C mode, set these bits to 000b (no delay).
b1
b1
b0
b0
U0SMR2 to U2SMR2
Symbol
SWC2
Symbol
NODC
U0SMR3 to U2SMR3
IICM2
STAC
CKPH
SDHI
SWC
CSC
ALS
DL0
DL1
DL2
(b7)
(b0)
(b2)
(b4)
Bit
Bit
-
-
-
-
Symbol
Symbol
I
Clock-synchronous
bit
SCL wait output bit
SDA output stop bit
UARTi initialization
bit
SCL wait output
bit 2
SDA output disable
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Clock phase set bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Clock output select
bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
SDAi digital delay
setup bits
2
C mode select bit 2
Bit Name
Bit Name
(1) (2)
01EEh, 01F2h, 01F6h
01EDh, 01F1h, 01F5h
See Table 15.12 I
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
0: Enabled
1: Disabled (high-impedance)
0 : Without clock delay
1 : With clock delay
0 : CLKi is CMOS output
1 : CLKi is N channel open-drain output
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
b7 b6 b5
Address
Address
Function
Function
2
C Mode Functions
After Reset
000X0X0Xb
X0000000b
After Reset
2
C mode.
15. Serial Interface
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
-
-
-
-