M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 250

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 19.13 Sub Modes of CAN Operation Mode
19.5.2 CAN Operation Mode
19.5.3 CAN Sleep Mode
19.5.4 CAN Interface Sleep Mode
CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to 0. If the Reset
bit is set to 0, check that the State_Reset bit in the CiSTR register is set to 0.
If 11 consecutive recessive bits are detected after entering CAN operation mode, the module initiates the
following functions:
Within CAN operation mode, the module may be in three different sub modes, depending on which type
of communication functions are performed:
Figure 19.13 shows the Sub Modes of CAN Operation Mode.
CAN sleep mode is activated by setting the Sleep bit to 1 in the CiCTLR register. It should never be
activated from CAN operation mode but only via CAN reset/initialization mode.
Entering CAN sleep mode instantly stops the clock supply to the module and thereby reduces power
dissipation.
CAN interface sleep mode is activated by setting the CCLK3 or CCLK7 bit in the CCLKR register to 1. It
should never be activated but only via CAN sleep mode.
Entering CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module and
thereby reduces power dissipation.
• The module's communication functions are released and it becomes an active node on the network
• Release the internal fault confinement logic including receive and transmit error counters. The module
• Module idle
• Module receives : The module receives a CAN message sent by another node.
• Module transmits : The module transmits a CAN message. The module may receive its own message
and may transmit and receive CAN messages.
may leave CAN operation mode depending on the error counts.
Apr 14, 2006
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: The modules receive and transmit sections are inactive.
transmission
simultaneously when the LoopBack bit in the CiCTLR register = 1 (Loop back mode
enabled).
TrmState, RecState: Bits in CiSTR register (i = 0, 1)
Start
Module transmits
TrmState = 1
RecState = 0
transmission
Finish
Lost in arbitration
Module idle
TrmState = 0
RecState = 0
Finish
reception
Module receives
TrmState = 0
RecState = 1
Detect
an SOF
19. CAN Module