M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 106

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 10.3 Settings of Interrupt Priority Levels
Bits ILVL2 to ILVL0 Interrupt Priority Level Priority Order
10.5.1 I Flag
10.5.2 IR Bit
10.5.3 Bits ILVL2 to ILVL0 and IPL
The I flag enables or disables the maskable interrupt. Setting the I flag to 1 (enabled) enables the
maskable interrupt. Setting the I flag to 0 (disabled) disables all maskable interrupts.
The IR bit is set to 1 (interrupt requested) when an interrupt request is generated. Then, when the inter-
rupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set to
0 (interrupt not requested).
The IR bit can be set to 0 in a program. Note that do not write 1 to this bit.
Interrupt priority levels can be set using bits ILVL2 to ILVL0.
Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
The I flag, IR bit, bits ILVL2 to ILVL0 and IPL are independent of each other. In no case do they affect one
another.
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
000b
001b
010b
011b
100b
101b
110b
111b
Apr 14, 2006
Level 0 (Interrupt disabled)
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
page 82 of 376
High
Low
-
Table 10.4 Interrupt Priority Levels Enabled by IPL
000b
001b
010b
011b
100b
101b
110b
111b
IPL
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
Enabled Interrupt Priority Levels
10. Interrupts