M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 402

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.00 Nov. 10, 2004
Rev.
Date
REVISION HISTORY
Page
38
39
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Table 7.1 Difference between Separate Bus and Multiplexed Bus is added.
Figure 7.1 CSR Register: NOTE 2 is revised.
Table 7.8 Software Wait Related Bits and Bus Cycles
Table 8.1 Clock Generating Circuit Specifications
Figure 8.1 Clock Generating Circuit: Block diagram (upper) is revised.
Figure 8.2 CM0 Register
Figure 8.3 CM1 Register: NOTE 3 of CM11 bit is deleted.
Figure 8.6 CCLKR Register: Location of NOTE 2 is changed and NOTE 3 is added.
Figure 8.7 PM2 Register: NOTE 2 is revised.
Figure 8.8 PLC0 Register: Function of 011b and 100b in PLC02 to PLC00 bits are revised
8.1.4 PLL Clock 11th line: 16 MHz is added to PLL clock frequency.
Table 8.2 Example for Setting PLL Clock Frequencies
Figure 8.11 Procedure to Use PLL Clock as CPU Clock Source
8.4.1.2 PLL Operation Mode: 1st line
Table 8.3 Setting Clock Related Bit and Modes
8.4.2 Wait Mode 4th line: "PLL clock" is deleted.
Table 8.4 Pin Status During Wait Mode
Table 8.5 Interrupts to Exit Wait Mode
8.4.3 Stop Mode
Table 8.6 Pin Status in Stop Mode
• Bus Cycle of SFR (PM20 = 0) is revised from "2 BCLK cycles" to "3 BCLK cycles".
• Bus Cycle of SFR (PM20 = 1) is revised from "3 BCLK cycles" to "2 BCLK cycles".
• From bottom to 5th item in CSR Register: The value is revised from "1" to "0".
• NOTE 5 is added.
• Clock Frequency in PLL Frequency Synthesizer: 16 MHz is added.
• Bit name of CM02 is revised.
• NOTE 6 (2) and NOTE 8 are revised.
• PLL clock = 16 MHz is added. (8✕2, 4✕4)
• 16 MHz is added to NOTE 1.
• 4th frame: “(To select a 16 MHz or higher PLL clock)” is revised to “(When PLL clock
• The main clock multiplied is revised from "by 2, 4, 6 or 8" to "by 2 or 4".
• CM21 bit in Low Power Dissipation Mode: Value is revised from "-" to "0".
• CM11 bit in Low-Speed Mode, Low Power Dissipation Mode, On-chip Oscillator Mode
• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from
• CAN0/1 Wake-up Interrupt: "in CAN sleep mode" is added.
• CAN0/1 Wake-up interrupt: "(when CAN sleep mode is selected)" is added.
• Memory Expansion Mode, Microprocessor Mode in ALE: Value is revised from
>16 MHz)”.
and On-chip Oscillator Low Power Dissipation Mode: Value is revised from "-" to "0".
"H" to "L".
" H" to "indeterminate".
M16C/6N Group (M16C/6N4) Hardware Manual
C-2
from "Multiply by 6 and Multiply by 8" to "Do not set a value".
Description
Summary