M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 57

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
5.2 Software Reset
5.3 Watchdog Timer Reset
5.4 Oscillation Stop Detection Reset
5.5 Internal Space
Figure 5.3 CPU Register Status After Reset
The MCU resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to 1 (MCU reset).
Then the MCU executes the program in an address determined by the reset vector.
Set the PM03 bit to 1 while the main clock is selected as the CPU clock and the main clock oscillation is stable.
In the software reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function Registers
(SFRs) for details.
Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.
The MCU resets pins, the CPU and SFR when the PM12 bit in the PM1 register is set to 1 (reset when
watchdog timer underflows) and the watchdog timer underflows. Then the MCU executes the program in an
address determined by the reset vector.
In the watchdog timer reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function
Registers (SFRs) for details.
Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.
The MCU resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is 0 (reset at
oscillation stop, re-oscillation detection), if it detects main clock oscillation circuit stop. Refer to 8.5 Oscillation
Stop and Re-Oscillation Detection Function for details.
In the oscillation stop detection reset, the MCU does not reset a part of the SFR. Refer to 4. Special Function
Registers (SFRs) for details.
Processor mode remains unchanged since bits PM01 to PM00 in the PM0 register are not reset.
Figure 5.3 shows CPU Register Status After Reset. Refer to 4. Special Function Registers (SFRs) for
SFR states after reset.
Apr 14, 2006
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Data Register (R0)
Data Register (R1)
Data Register (R2)
Data Register (R3)
Address Register (A0)
Address Register (A1)
Frame Base Register (FB)
Interrupt Table Register (INTB)
Program Counter (PC)
User Stack Pointer (USP)
Interrupt Stack Pointer (ISP)
Static Base Register (SB)
Flag Register (FLG)
5. Resets