M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 199

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
15.1.3.7 ACK and NACK
15.1.3.8 Initialization of Transmission/Reception
If the STSPSEL bit in the UiSMR4 register is set to 0 (start and stop conditions not generated) and the
ACKC bit in the UiSMR4 register is set to 1 (ACK data output), the value of the ACKD bit in the UiSMR4
register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge
of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the
rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the DMA1 request source, a DMA transfer can be activated by detection of an
acknowledge.
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial interface
operates as described below.
• The transmit shift register is initialized, and the content of the UiTB register is transferred to the transmit
• The receive shift register is initialized, and the serial interface starts receiving data synchronously with
• The SWC bit is set to 1 (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
Note that when UARTi transmission/reception is started using this function, the TI bit does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
shift register. In this way, the serial interface starts transmitting data synchronously with the next clock
pulse applied. However, the UARTi output value does not change state and remains the same as
when a start condition was detected until the first bit of data is output synchronously with the input
clock.
the next clock pulse applied.
falling edge of the 9th clock pulse.
Apr 14, 2006
page 175 of 376
15. Serial Interface