M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 210

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.33 SIM Interface Connection
Figure 15.34 Parity Error Signal Output Timing
Figure 15.33 shows the SIM Interface Connection. Connect TXD2 and RXD2 and apply pull-up.
15.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to 1 (output enabled).
The parity error signal is output when a parity error is detected while receiving data. This is achieved by
pulling the TXD2 output low with the timing shown in Figure 15.32. If the U2RB register is read while
outputting a parity error signal, the PER bit in the U2RB register is set to 0 (no parity error) and at the
same time the TXD2 output is returned high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer
clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned
can be determined by reading the port that shares the UXD2 pin in a transmission-finished interrupt
routine.
Figure 15.34 shows the output timing of the parity error signal
Apr 14, 2006
NOTE:
U2C1 register
This timing diagram applies to the case where the direct format is
implemented.
1: The output of MCU is in the high-impedance state (pulled up externally).
Transfer
RI bit in
RXD2
TXD2
clock
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"H"
"H"
"H"
"L"
"L"
"L"
1
0
MCU
RXD2
TXD2
ST
D0
D1
D2
D3
(NOTE 1)
D4
SIM card
D5
D6
D7
ST: Start bit
P: Even Parity
SP: Stop bit
P
SP
15. Serial Interface