M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 206

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 15.31 Bus Collision Detect Function-Related Bits
NOTES:
(1) The ABSCS bit in UiSMR register (bus collision detect sampling clock select)
(2) The ACSE bit in UiSMR register (auto clear of transmit enable bit)
(3) The SSS bit in UiSMR register (transmit start condition select)
i = 0 to 2
This diagram applies to the case where IOPOL bit =1 (reversed).
Transfer clock
Transfer clock
RXDi
Timer Aj
TXDi
TXDi
TXDi
RXDi
TXDi
IR bit in
UiBCNIC register
TE bit in
UiC1 register
CLKi
RXDi
Transfer clock
1.The falling edge of RXDi when IOPOL bit = 0; the rising edge of RXDi when IOPOL bit = 1.
2.The transmit condition must be met before the falling edge
Apr 14, 2006
If SSS bit = 0, the serial interface starts transmitting data one transfer clock cycle after the transmission enable condition is met
If SSS bit = 1, the serial interface starts transmitting data at the rising edge
Transmission enable condition is met
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timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(NOTE 2)
If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock
ST
ST
Trigger signal is applied to the TAjIN pin
ST
ST
D0
D0
D0
D0
D1
D1
D1
D1
D2
D2
(1)
of RXDi.
D2
D2
If ABSCS bit = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
D3
D3
D3
D3
D4
D4
D4
D4
(1)
of RXDi
D5
D5
D5
D5
D6
D6
D6
D6
If the ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to 0
(transmission disabled) when
the IR bit in the UiBCNIC register = 1
(unmatching detected).
D7
D7
D7
D7
D8
D8
D8
D8
15. Serial Interface
SP
SP
SP
SP
.