M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 191

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Table 15.10 I
i = 0 to 2
NOTES:
Transfer data format
Transfer clock
Transmit start condition
Receive start condition
Error detection
Select function
15.1.3 Special Mode 1 (I
Interrupt request
generation timing
I
Specifications. Figure 15.23 shows the I
Used and Setting in I
to UiRB Register and Interrupt Timing.
As shown in Table 15.12, the MCU is placed in I
IICM bit to 1. Because SDAi transmit output has a delay circuit attached, SDAi output does not change
state until SCLi goes low and remains stably low.
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2. If an overrun error occurs, the value of UiRB register will be undefined. The IR bit in the SiRIC register
2
C mode is provided for use as a simplified I
remains unchanged.
Apr 14, 2006
Item
2
C Mode Specifications
page 167 of 376
2
C Mode. Table 15.12 lists the I
Transfer data length: 8 bits
• During master
• During slave
Before transmission can start, meet the following requirements
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Before reception can start, meet the following requirements
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Overrun error
• Arbitration lost
• SDAi digital delay
• Clock phase setting
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/(2(n+1))
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
The CKDIR bit = 1 (external clock) : Input from SCLi pin
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
Timing at which the ABT bit in the UiRB register is updated can be selected
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
With or without clock delay selectable
2
C Mode)
(2)
2
C Mode Block Diagram. Table 15.11 lists the Registers to be
2
C interface compatible mode. Table 15.10 lists the I
2
C mode by setting bits SMD2 to SMD0 to 010b and the
2
C Mode Functions. Figure 15.24 shows the Transfer
Specification
(1)
(1)
15. Serial Interface
2
C Mode