M306N4FGGP#U3 Renesas Electronics America, M306N4FGGP#U3 Datasheet - Page 259

• Manufacturer Part Number: M306N4FGGP#U3
• Description: IC M16C/6N4 MCU FLASH 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/6Nr

Specifications of M306N4FGGP#U3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 24MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: M16C
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 87
• Interface Type: I2C/UART
• On-chip Adc: 26-chx10-bit
• On-chip Dac: 2-chx8-bit
• Number Of Timers: 11
• For Use With: R0K3306NKS001BE - KIT DEV RSK RSK-M16C/6NKR0K3306NKS000BE - KIT DEV RSK RSK-M16C/6NK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M16C/6N Group (M16C/6N4)
Rev.2.40
REJ09B0009-0240
Figure 19.20 Timing of Receive Data Frame Sequence
19.15.1 Reception
Figure 19.20 shows the Timing of Receive Data Frame Sequence. Figure 19.20 shows the behavior of
the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj
register (i = 0, 1, j = 0 to 15) and leads to losing/overwriting of the first message.
(1) On monitoring a SOF on the CAN bus the RecState bit in the CiSTR register becomes 1 (CAN module
(2) After successful reception of the message, the NewData bit in the CiMCTLj register of the receiving
(3) When the interrupt enable bit in the CiICR register of the receiving slot = 1 (interrupt enabled), the
(4) Read the message out of the slot after setting the New Data bit to 0 (the content of the slot is read or
(5) When next CAN message is received before the NewData bit is set to 0 by a program or a receive
reception interrupt
i = 0, 1
j = 0 to 15
CANi successful
is receiver) immediately, given the module has no transmission pending.
slot becomes 1 (stored new data in slot). The InvalData bit in the CiMCTLj register becomes 1
(message is being updated) at the same time and the InvalData bit becomes 0 (message is valid) again
after the complete message was transferred to the slot.
CANi successful reception interrupt request is generated and the MBOX bit in the CiSTR register is
changed. It shows the slot number where the message was stored and the RecSucc bit in the CiSTR
register is active.
still under processing by the CPU) by a program.
request to a slot is canceled, the MsgLost bit in the CiMCTLj register is set to 1 (message has been
overwritten). The new received message is transferred to the slot. Generating of an interrupt request
and change of the CiSTR register are same as in 3).
Apr 14, 2006
InvalData bit
NewData bit
RecState bit
RecSucc bit
MsgLost bit
RecReq bit
MBOX bit
CAN bus
page 235 of 376
SOF
(1)
ACK
EOF
(2)
(2)
(3)
IFS
SOF
Receive slot No.
(4)
ACK
EOF
(5)
(5)
(5)
19. CAN Module
IFS