MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 81

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

2.3.2.6
The general guideline is that Flash protection can only be added and not removed.
valid transitions between Flash protection scenarios. Any attempt to write an invalid scenario to the
FPROT register will be ignored and the FPROT register will remain unchanged. The contents of the
FPROT register reflect the active protection scenario. See the FPHS and FPLS descriptions for additional
restrictions.
2.3.2.7
The FSTAT register defines the operational status of the module.
Freescale Semiconductor
Reset
Reset
W
W
R
R
CBEIF
CBEIF
Flash Protection Restrictions
Flash Status Register (FSTAT)
7
1
7
1
1
Allowed transitions marked with X.
Protection
Scenario
From
= Unimplemented or Reserved
= Unimplemented or Reserved
0
1
2
3
4
5
6
7
Figure 2-10. Flash Status Register (FSTAT - Special Mode)
CCIF
CCIF
Figure 2-9. Flash Status Register (FSTAT - Normal Mode)
6
1
6
1
Table 2-13. Flash Protection Scenario Transitions
X
X
0
PVIOL
PVIOL
MC9S12NE64 Data Sheet, Rev. 1.1
5
0
5
0
1
X
X
X
X
ACCERR
ACCERR
X
X
X
X
2
To Protection Scenario
4
0
4
0
X
X
X
X
X
X
X
X
3
3
0
0
3
0
0
X
X
X
X
4
1
5
X
X
BLANK
BLANK
2
0
2
0
Memory Map and Register Definition
X
X
6
Table 2-13
FAIL
X
7
1
0
0
1
0
specifies all
0
0
0
0
0
0
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