MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 201

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.4
This section provides a complete functional description of the timer TIM16B4CV1 block. Please refer to
the detailed timer block diagram in
Freescale Semiconductor
PACLK/65536
PACLK/256
Functional Description
Bus Clock
PAOVF
INTERRUPT
REQUEST
PR[2:1:0]
16-BIT COMPARATOR
16-BIT COMPARATOR
EDG4A
TCNT(hi):TCNT(lo)
PAOVF
PRESCALER
16-BIT COUNTER
PAOVI
CHANNEL7
CHANNEL 4
PACNT(hi):PACNT(lo)
TC4
TC7
16-BIT COUNTER
EDG7A
EDG7B
EDG4B
INTERRUPT
PAOVI
LOGIC
PACLK/65536
PAOVF
PACLK/256
Figure 6-26. Detailed Timer Block Diagram
PACLK
CLEAR COUNTER
Figure 6-26
DETECT
TE
DETECT
EDGE
EDGE
MC9S12NE64 Data Sheet, Rev. 1.1
PAIF
C4F
C7F
PAI
PACLK
MUX
OM:OL4
OM:OL7
TOV4
TOV7
CLK[1:0]
as necessary.
DIVIDE-BY-64
TOF
TOI
PAMOD
PEDGE
IOC4
CxF
CxI
C4F
PAE
C7F
IOC7
INTERRUPT
LOGIC
IOC4 PIN
IOC7 PIN
LOGIC
LOGIC
DETECT
EDGE
PAIF
channel 7 output
compare
TCRE
CH. 4 COMPARE
CH. 4 CAPTURE
CH. 7 COMPARE
CH.7 CAPTURE
PA INPUT
Functional Description
Bus Clock
IOC4 PIN
IOC7 PIN
TOF
201