MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 424
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MC9S12NE64VTU
Manufacturer Part Number
MC9S12NE64VTU
Description
IC MCU 25MHZ ETHERNET/PHY 80TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTU
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 16 Module Mapping Control (MMCV4)
16.1.2
Some of the registers operate differently depending on the mode of operation (i.e., normal expanded wide,
special single chip, etc.). This is best understood from the register descriptions.
16.2
All interfacing with the MMC sub-block is done within the core, it has no external signals.
16.3
A summary of the registers associated with the MMC sub-block is shown in
descriptions of the registers and bits are given in the subsections that follow.
16.3.1
424
•
•
•
•
•
•
•
•
•
•
Memory mapping control and selection based upon address decode and system operating mode
Core address bus control
Core data bus control and multiplexing
Core security state decoding
Emulation chip select signal generation (ECS)
External chip select signal generation (XCS)
Internal memory expansion
External stretch and ROM mapping control functions via the MISC register
Reserved registers for test purposes
Configurable system memory options defined at integration of core into the system-on-a-chip
(SoC).
External Signal Description
Memory Map and Register Definition
Address
Offset
Modes of Operation
Module Memory Map
.
.
.
.
Initialization of Internal RAM Position Register (INITRM)
Initialization of Internal Registers Position Register (INITRG)
Initialization of Internal EEPROM Position Register (INITEE)
Miscellaneous System Control Register (MISC)
Reserved
Reserved
MC9S12NE64 Data Sheet, Rev. 1.1
Table 16-1. MMC Memory Map
Register
.
.
.
.
Figure
16-2. Detailed
Freescale Semiconductor
Access
R/W
R/W
R/W
R/W
—
—
—
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