MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 308

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 11 Ethernet Media Access Controller (EMACV1)
11.1.2
11.2
The EMAC module supports the medium-independent interface (MII) which requires 18 input/output
(I/O) pins. The transmit and receive functions require seven signals each (four data signals, a delimiter,
error, and clock). In addition, there are two signals which indicate the status of the media (one indicates
the presence of a carrier and the other indicates that a collision has occurred). The MII management
function requires the remaining two signals, MII_MDC and MII_MDIO. Each MII signal is described
below. These signals are available externally only when the EMAC is enabled in external PHY mode. MII
signals are available only in certain MCU modes.
308
RAM
INTERFACE
SIGNALS
MCU
INTERFACE
RAM
INTERFACE
SIGNALS
IP BUS
SIGNALS
External Signal Description
Block Diagram
MAC FLOW CONTROL
EMAC
RX BUFFER B
RX BUFFER A
INTERFACE
INTERFACE
TX BUFFER
INTERFACE
REGISTERS
IP BUS
Figure 11-1. EMAC Block Diagram
MC9S12NE64 Data Sheet, Rev. 1.1
TRANSMITTER
MANAGEMENT
RECEIVER
MII
Freescale Semiconductor
INTERFACE
MII_RXCLK
MII_RXDV
MII_RXD[3:0]
MII_RXER
MII_TXCLK
MII_TXEN
MII_TXD[3:0]
MII_TXER
MII_CRS
MII_COL
MII_MDC
MII_MDIO
MII