MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 119

• Manufacturer Part Number: MC9S12NE64VTU
• Description: IC MCU 25MHZ ETHERNET/PHY 80TQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12NE64VTU

• Mfg Application Notes: MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.375 V ~ 3.465 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 16 bit
• Operating Supply Voltage: - 0.3 V to + 3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 65 C
• On-chip Adc: 10 bit
• For Use With: EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.3.2.2.7
Read:Anytime.
Write:Anytime.
This register configures the output pins as wired-or. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the SPI and SCI outputs and allows a
multipoint connection of several serial modules. These bits have no influence on pins used as inputs.
WOMS[7:0] — Wired-Or Mode Port S
3.3.2.3
3.3.2.3.1
Read:Anytime.
Write:Anytime.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read. The EMAC MII external interface takes precedence over
general-purpose I/O function if the EMAC module is enabled in external PHY mode. If the EMAC is
enabled PG[6:0] pins become inputs MII_RXER, MII_RXDV, MII_RXCLK, MII_RXD[3:0]. Please refer
to the EMAC block description chapter for details.
Freescale Semiconductor
1 = Open-drain mode enabled for output buffers.
0 = Open-drain mode disabled for output buffers.
Module Base + $10
Module Base + $E
Reset:
EMAC
Read:
Write:
Reset:
Read:
Write:
KWU
Port G Registers
Wired-Or Mode Register (WOMS)
I/O Register (PTG)
WOMS7
PTG7
Bit 7
Bit 7
—
—
0
MII_RXER MII_RXDV MII_RXCLK MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0
Figure 3-14. Port S Wired-Or Mode Register (WOMS)
WOMS6
PTG6
6
0
6
0
Figure 3-15. Port G I/O Register (PTG)
WOMS5
MC9S12NE64 Data Sheet, Rev. 1.1
PTG5
5
0
5
0
WOMS4
PTG4
4
0
4
0
KWG
WOMS3
PTG3
3
0
3
0
WOMS2
PTG2
2
0
2
0
Memory Map and Register Descriptions
WOMS1
PTG1
1
0
1
0
WOMS0
PTG0
Bit 0
Bit 0
0
0
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