MC9S12NE64VTU Freescale Semiconductor, MC9S12NE64VTU Datasheet - Page 128
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MC9S12NE64VTU
Manufacturer Part Number
MC9S12NE64VTU
Description
IC MCU 25MHZ ETHERNET/PHY 80TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTU
Mfg Application Notes
MC9S12NE64 Integrated Ethernet Controller Implementing an Ethernet Interface with the MC9S12NE64 Web Server Development with MC9S12NE64 and Open TCP
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
70
Number Of Timers
16 bit
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Chapter 3 Port Integration Module (PIM9NE64V1)
3.3.2.5.3
Read:Anytime.
Write:Anytime.
This register configures port pins J[7:6]and PJ[3:0] as either input or output.
DDRJ[7:6][3:0] — Data Direction Port J
Due to internal synchronization circuits, it can take up to 2 bus cycles until the correct value is read on PTJ
or PTIJ registers, when changing the DDRJ register.
If the IIC is enabled, It controls the direction of SCL and SDA and the corresponding DDRJ[7:6] bits have
no effect on their I/O direction. Refer to the IIC block description chapter for details.
If the EMAC MII external interface is enabled, It controls the direction of MDC, MDIO, CRS and COL
and the corresponding DDRJ[3:0] bits have no effect on their I/O direction. Refer to the EMAC block
description chapter for details.
3.3.2.5.4
Read:Anytime.
Write:Anytime.
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
RDRJ[7:6][3:0] — Reduced Drive Port J
128
1 = Associated pin is configured as output.
0 = Associated pin is configured as input.
1 = Associated pin drives at about 1/3 of the full drive strength.
0 = Full drive strength at output.
Module Base + $22
Module Base + $23
Reset:
Reset:
Read:
Read:
Write:
Write:
Data Direction Register (DDRJ)
Reduced Drive Register (RDRJ)
DDRJ7
RDRJ7
Bit 7
Bit 7
0
0
= Reserved or unimplemented
= Reserved or unimplemented
DDRJ6
RDRJ6
Figure 3-34. Port J Reduced Drive Register (RDRJ)
Figure 3-33. Port J Data Direction Register (DDRJ)
6
0
6
0
MC9S12NE64 Data Sheet, Rev. 1.1
—
—
5
0
5
0
—
—
4
0
4
0
DDRJ3
RDRJ3
3
0
3
0
DDRJ2
RDRJ2
2
0
2
0
DDRJ1
RDRJ1
1
0
1
0
Freescale Semiconductor
DDRJ0
RDRJ0
Bit 0
Bit 0
0
0
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